1. Field of the Invention
The invention relates to a method of fabricating a capacitor, and more particularly to a method of fabricating a 3-D capacitor of dynamic random access memory (DRAM).
2. Description of the Related Art
The lower electrode and the upper electrode of DRAM capacitor normally use polysilicon to serve as conductive material. However, the V.sub.bias applied on the upper electrode easily causes holes to form between the lower electrode and the capacitor dielectric layer. The holes compensate N-type impurities originally doped inside the polysilicon layer serving as a lower electrode. Consequently, a depletion region is formed on the upper surface of the lower electrode, thus forming an additional dielectric layer. In other words, the thickness of the overall dielectric layer is thickened, the surface of the capacitor dielectric layer is decreased and the charge storage capacity of the capacitor is reduced.
The depletion effect can be reduced by increasing the surface doping concentration of the lower electrode. In the traditional method, an ion implantation step is performed on the lower electrode, thereby implanting ions into the lower electrode to increase the surface doping concentration of the lower electrode. However, it is difficult for this method to solve the depletion problem occurring on the sidewall of the capacitor if a high, 3-D, stacked capacitor or a selective Hemisphere Grain (HSG) is used. This is because the implanted ions can barely reach the sidewall of the capacitor under the limitations of the implant angle and the shadowing effect. Therefore, the ion implantation to increase the surface doping concentration cannot thoroughly solve the depletion problem. In addition, the doping concentration on the lower electrode is not uniform, which leads to an unstable charge storage capacity of the capacitor. As a result, the reliability of the capacitor is reduced.